A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line

A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line

Duty-cycle distortion may occur due to variations in the process, voltage, and temperature, or if the clock signal passes through clock buffers. To compensate duty-cycle distortion, a digital duty-cycle corrector (DCC) with counter-based half-cycle delay line (HCDL) is introduced. The HCDL of conven...

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Bibliographic Details
Main Authors: Jaewook Kim, Jaekwang Yun, Joo-Hyung Chae, Suhwan Kim
Format: Article
Language:English
Published: IEEE 2023-01-01
Series:IEEE Access
Subjects:
Memory interface
ADC interface
digital duty-cycle corrector (DCC)
half-cycle delay line (HCDL)
Online Access:https://ieeexplore.ieee.org/document/10082909/

Internet

https://ieeexplore.ieee.org/document/10082909/

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