A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line
Duty-cycle distortion may occur due to variations in the process, voltage, and temperature, or if the clock signal passes through clock buffers. To compensate duty-cycle distortion, a digital duty-cycle corrector (DCC) with counter-based half-cycle delay line (HCDL) is introduced. The HCDL of conven...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2023-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10082909/ |
| _version_ | 1797855387180859392 |
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| author | Jaewook Kim Jaekwang Yun Joo-Hyung Chae Suhwan Kim |
| author_facet | Jaewook Kim Jaekwang Yun Joo-Hyung Chae Suhwan Kim |
| author_sort | Jaewook Kim |
| collection | DOAJ |
| description | Duty-cycle distortion may occur due to variations in the process, voltage, and temperature, or if the clock signal passes through clock buffers. To compensate duty-cycle distortion, a digital duty-cycle corrector (DCC) with counter-based half-cycle delay line (HCDL) is introduced. The HCDL of conventional edge combiner type DCC requires a large area and make the DCC unsuitable for applications that operate in a wide-range frequency. The proposed counter-based HCDL reduces the silicon cost by repeating the delay line, while maintaining the performance of conventional DCC. A prototype chip fabricated in a 65nm CMOS process has an area of 0.0064mm2 and consumes 2.1mW at 1.6GHz. The measurement results show that the duty-cycle error is less than 0.89% over an input duty-cycle range of 20-80% for 50-1600MHz. |
| first_indexed | 2024-04-09T20:21:49Z |
| format | Article |
| id | doaj.art-2d870e167b0442a287836ab67c224b72 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-09T20:21:49Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-2d870e167b0442a287836ab67c224b722023-03-30T23:00:44ZengIEEEIEEE Access2169-35362023-01-0111305553056110.1109/ACCESS.2023.326230710082909A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay LineJaewook Kim0Jaekwang Yun1Joo-Hyung Chae2https://orcid.org/0000-0001-6354-5612Suhwan Kim3https://orcid.org/0000-0001-9107-2963Department of Electrical and Computer Engineering, Seoul National University, Seoul, South KoreaDepartment of Electrical and Computer Engineering, Seoul National University, Seoul, South KoreaDepartment of Electronics and Communications Engineering, Kwangwoon University, Seoul, South KoreaDepartment of Electrical and Computer Engineering, Seoul National University, Seoul, South KoreaDuty-cycle distortion may occur due to variations in the process, voltage, and temperature, or if the clock signal passes through clock buffers. To compensate duty-cycle distortion, a digital duty-cycle corrector (DCC) with counter-based half-cycle delay line (HCDL) is introduced. The HCDL of conventional edge combiner type DCC requires a large area and make the DCC unsuitable for applications that operate in a wide-range frequency. The proposed counter-based HCDL reduces the silicon cost by repeating the delay line, while maintaining the performance of conventional DCC. A prototype chip fabricated in a 65nm CMOS process has an area of 0.0064mm2 and consumes 2.1mW at 1.6GHz. The measurement results show that the duty-cycle error is less than 0.89% over an input duty-cycle range of 20-80% for 50-1600MHz.https://ieeexplore.ieee.org/document/10082909/Memory interfaceADC interfacedigital duty-cycle corrector (DCC)half-cycle delay line (HCDL) |
| spellingShingle | Jaewook Kim Jaekwang Yun Joo-Hyung Chae Suhwan Kim A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line IEEE Access Memory interface ADC interface digital duty-cycle corrector (DCC) half-cycle delay line (HCDL) |
| title | A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line |
| title_full | A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line |
| title_fullStr | A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line |
| title_full_unstemmed | A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line |
| title_short | A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line |
| title_sort | 50 x2013 1600 mhz wide x2013 range digital duty x2013 cycle corrector with counter x2013 based half x2013 cycle delay line |
| topic | Memory interface ADC interface digital duty-cycle corrector (DCC) half-cycle delay line (HCDL) |
| url | https://ieeexplore.ieee.org/document/10082909/ |
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