A 50–1600 MHz Wide–Range Digital Duty–Cycle Corrector With Counter–Based Half–Cycle Delay Line
Duty-cycle distortion may occur due to variations in the process, voltage, and temperature, or if the clock signal passes through clock buffers. To compensate duty-cycle distortion, a digital duty-cycle corrector (DCC) with counter-based half-cycle delay line (HCDL) is introduced. The HCDL of conven...
Main Authors: | Jaewook Kim, Jaekwang Yun, Joo-Hyung Chae, Suhwan Kim |
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Format: | Article |
Language: | English |
Published: |
IEEE
2023-01-01
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Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/10082909/ |
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