A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architec...

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Bibliographic Details
Main Authors: Leandro D. Medus, Taras Iakymchuk, Jose Vicente Frances-Villora, Manuel Bataller-Mompean, Alfredo Rosado-Munoz
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
Feedforward neural networks - FFNN
systolic hardware architecture
FPGA implementation
neural network acceleration
deep neural networks
Online Access:https://ieeexplore.ieee.org/document/8731886/

Internet

https://ieeexplore.ieee.org/document/8731886/

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