An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder
A hardware-efficient implementation of a Low-Density Parity-Check (LDPC) decoder is presented in this paper. The proposed decoder design is based on the Hybrid Offset Min-Sum (HOMS) algorithm. In the check node processing of this decoder, only the first minimum is computed instead of the first two m...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2023-08-01
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| Series: | Electronics |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9292/12/17/3667 |