A New VLSI Architecture for High-Performance Parallel Turbo Decoder

A New VLSI Architecture for High-Performance Parallel Turbo Decoder

Recent wireless communications demand maximum achievable data rates without intervention. The channel decoder in the physical layer would support such high data rates with a flexible hardware structure. The turbo channel decoder offers flexible hardware architecture and reliable decoding, but the t...

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Bibliographic Details
Main Authors: sujatha elukuru, SUBHAS CHENNAPALLI, GIRIPRASAD MAHENDRA NANJAPPA
Format: Article
Language:English
Published: IIUM Press, International Islamic University Malaysia 2022-07-01
Series:International Islamic University Malaysia Engineering Journal
Subjects:
Turbo decoder
MAP decoder
VLSI
Interleaver
FPGA
Online Access:https://journals.iium.edu.my/ejournal/index.php/iiumej/article/view/2272

Internet

https://journals.iium.edu.my/ejournal/index.php/iiumej/article/view/2272

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