An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation

An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation

This paper introduces a design and on-chip verification framework for IPCores in FPGA platforms. The methodology of the proposed framework is based on the development of a high level software model, an HDL description of the IPCore and the verification of the system under test by the Autotest Core,...

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Bibliographic Details
Main Authors: German Cano-Quiveu, Paulino Ruiz-De-Clavijo-Vazquez, Manuel J. Bellido-Diaz, David Guerrero-Martos, Julian Viejo-Cortes, Jorge Juan-Chico
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
FPGA
framework
HDL
IoT
IPCore
on-chip
Online Access:https://ieeexplore.ieee.org/document/9632568/

Internet

https://ieeexplore.ieee.org/document/9632568/

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