An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation
This paper introduces a design and on-chip verification framework for IPCores in FPGA platforms. The methodology of the proposed framework is based on the development of a high level software model, an HDL description of the IPCore and the verification of the system under test by the Autotest Core,...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2021-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9632568/ |
| _version_ | 1819004263460765696 |
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| author | German Cano-Quiveu Paulino Ruiz-De-Clavijo-Vazquez Manuel J. Bellido-Diaz David Guerrero-Martos Julian Viejo-Cortes Jorge Juan-Chico |
| author_facet | German Cano-Quiveu Paulino Ruiz-De-Clavijo-Vazquez Manuel J. Bellido-Diaz David Guerrero-Martos Julian Viejo-Cortes Jorge Juan-Chico |
| author_sort | German Cano-Quiveu |
| collection | DOAJ |
| description | This paper introduces a design and on-chip verification framework for IPCores in FPGA platforms. The methodology of the proposed framework is based on the development of a high level software model, an HDL description of the IPCore and the verification of the system under test by the Autotest Core, an on-chip verification core developed for this framework. The test pattern generation is done at the high level in software and used throughout the design and verification process. HDL simulation results can then be compared to on-chip results and get performance measurements from the Autotest Core. The Off-line testing is possible by using standard low-cost Flash storage (SD card). The proposed framework and methodology applied to PRESENT and SPONGENT cryptographic algorithms has shown over two orders of magnitude better performance than commercial tools like Xilinx’s VIO and a hardware footprint of the verification cored below 3% of the available FPGA resources. |
| first_indexed | 2024-12-20T23:34:07Z |
| format | Article |
| id | doaj.art-35005663a3524faf91c36de35f85f9d7 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-20T23:34:07Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-35005663a3524faf91c36de35f85f9d72022-12-21T19:23:15ZengIEEEIEEE Access2169-35362021-01-01916138316139410.1109/ACCESS.2021.31321889632568An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance EvaluationGerman Cano-Quiveu0https://orcid.org/0000-0002-8963-0855Paulino Ruiz-De-Clavijo-Vazquez1Manuel J. Bellido-Diaz2https://orcid.org/0000-0002-5092-6042David Guerrero-Martos3Julian Viejo-Cortes4https://orcid.org/0000-0001-7543-5082Jorge Juan-Chico5Department of Electronic Technology, University of Seville, Seville, SpainDepartment of Electronic Technology, University of Seville, Seville, SpainDepartment of Electronic Technology, University of Seville, Seville, SpainDepartment of Electronic Technology, University of Seville, Seville, SpainDepartment of Electronic Technology, University of Seville, Seville, SpainDepartment of Electronic Technology, University of Seville, Seville, SpainThis paper introduces a design and on-chip verification framework for IPCores in FPGA platforms. The methodology of the proposed framework is based on the development of a high level software model, an HDL description of the IPCore and the verification of the system under test by the Autotest Core, an on-chip verification core developed for this framework. The test pattern generation is done at the high level in software and used throughout the design and verification process. HDL simulation results can then be compared to on-chip results and get performance measurements from the Autotest Core. The Off-line testing is possible by using standard low-cost Flash storage (SD card). The proposed framework and methodology applied to PRESENT and SPONGENT cryptographic algorithms has shown over two orders of magnitude better performance than commercial tools like Xilinx’s VIO and a hardware footprint of the verification cored below 3% of the available FPGA resources.https://ieeexplore.ieee.org/document/9632568/FPGAframeworkHDLIoTIPCoreon-chip |
| spellingShingle | German Cano-Quiveu Paulino Ruiz-De-Clavijo-Vazquez Manuel J. Bellido-Diaz David Guerrero-Martos Julian Viejo-Cortes Jorge Juan-Chico An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation IEEE Access FPGA framework HDL IoT IPCore on-chip |
| title | An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation |
| title_full | An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation |
| title_fullStr | An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation |
| title_full_unstemmed | An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation |
| title_short | An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation |
| title_sort | integrated digital system design framework with on chip functional verification and performance evaluation |
| topic | FPGA framework HDL IoT IPCore on-chip |
| url | https://ieeexplore.ieee.org/document/9632568/ |
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