3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET
In this study, we propose a self-aligned stacked Ge nanowire (NW) p-type gate-all-around field-effect transistor (pGAAFET) on Si nFinFET of single gate complementary FET (CFET). The self-aligned stacked Ge NW pGAAFET on Si nFinFET of single gate CFET device is fabricated on a SOI wafer. The CFET dev...
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10233696/ |
| _version_ | 1797357964905938944 |
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| author | Yi-Wen Lin Shan-Wen Lin Bo-An Chen Chong-Jhe Sun Siao-Cheng Yan Guang-Li Luo Yung-Chun Wu Fu-Ju Hou |
| author_facet | Yi-Wen Lin Shan-Wen Lin Bo-An Chen Chong-Jhe Sun Siao-Cheng Yan Guang-Li Luo Yung-Chun Wu Fu-Ju Hou |
| author_sort | Yi-Wen Lin |
| collection | DOAJ |
| description | In this study, we propose a self-aligned stacked Ge nanowire (NW) p-type gate-all-around field-effect transistor (pGAAFET) on Si nFinFET of single gate complementary FET (CFET). The self-aligned stacked Ge NW pGAAFET on Si nFinFET of single gate CFET device is fabricated on a SOI wafer. The CFET device is fully compatible with current Si technology platform using alternating anisotropic and isotropic dry etching process. The Ge NW pGAAFET presents an on-state current (ION) of <inline-formula> <tex-math notation="LaTeX">$166 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">${\mathrm{ V}}_{\mathrm{ D}}\,\,=$ </tex-math></inline-formula> VG-VTH <inline-formula> <tex-math notation="LaTeX">$=\,\,-0.5$ </tex-math></inline-formula> V and shows minimum subthreshold swing (SSmin) of 79, 91 mV/dec, and ION/IOFF of <inline-formula> <tex-math notation="LaTeX">$3.03\times10\,\,^{\mathrm{ 5}}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$3.4\times 10^{4}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">${\mathrm{ V}}_{\mathrm{ D}}\,\,=\,\,-0.05$ </tex-math></inline-formula> V and −0.5 V, respectively. The Si nFinFET presents an <inline-formula> <tex-math notation="LaTeX">${\mathrm{ I}}_{\mathrm{ ON}}$ </tex-math></inline-formula> of <inline-formula> <tex-math notation="LaTeX">$60.4 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">${\mathrm{ V}}_{\mathrm{ D}}\,\,=$ </tex-math></inline-formula> VG-VTH = 0.5 V and shows <inline-formula> <tex-math notation="LaTeX">${\mathrm{ SS}}_{\min }$ </tex-math></inline-formula> of 91, 101 mV/dec, and ION/IOFF of <inline-formula> <tex-math notation="LaTeX">$9.01\times10\,\,^{\mathrm{ 4}}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$5.62\times 10^{5}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">${\mathrm{ V}}_{\mathrm{ D}}\,\,=$ </tex-math></inline-formula> 0.05 V and 0.5 V, respectively. The proposed CFET can simplify the process and shows promising potential for extending scaling beyond the technology node. |
| first_indexed | 2024-03-08T14:52:13Z |
| format | Article |
| id | doaj.art-3577e1f2e6c947749d4160e51b7f0709 |
| institution | Directory Open Access Journal |
| issn | 2168-6734 |
| language | English |
| last_indexed | 2024-03-08T14:52:13Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj.art-3577e1f2e6c947749d4160e51b7f07092024-01-11T00:01:38ZengIEEEIEEE Journal of the Electron Devices Society2168-67342023-01-011148048410.1109/JEDS.2023.3309812102336963-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFETYi-Wen Lin0https://orcid.org/0009-0002-5242-9362Shan-Wen Lin1Bo-An Chen2Chong-Jhe Sun3https://orcid.org/0000-0003-2856-7458Siao-Cheng Yan4https://orcid.org/0000-0002-1030-3481Guang-Li Luo5https://orcid.org/0000-0001-9429-4342Yung-Chun Wu6https://orcid.org/0000-0001-9409-6792Fu-Ju Hou7https://orcid.org/0000-0001-8288-2542Department of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanTaiwan Semiconductor Research Institute, Hsinchu, TaiwanDepartment of Engineering and System Science, National Tsing Hua University, Hsinchu, TaiwanTaiwan Semiconductor Research Institute, Hsinchu, TaiwanIn this study, we propose a self-aligned stacked Ge nanowire (NW) p-type gate-all-around field-effect transistor (pGAAFET) on Si nFinFET of single gate complementary FET (CFET). The self-aligned stacked Ge NW pGAAFET on Si nFinFET of single gate CFET device is fabricated on a SOI wafer. The CFET device is fully compatible with current Si technology platform using alternating anisotropic and isotropic dry etching process. The Ge NW pGAAFET presents an on-state current (ION) of <inline-formula> <tex-math notation="LaTeX">$166 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">${\mathrm{ V}}_{\mathrm{ D}}\,\,=$ </tex-math></inline-formula> VG-VTH <inline-formula> <tex-math notation="LaTeX">$=\,\,-0.5$ </tex-math></inline-formula> V and shows minimum subthreshold swing (SSmin) of 79, 91 mV/dec, and ION/IOFF of <inline-formula> <tex-math notation="LaTeX">$3.03\times10\,\,^{\mathrm{ 5}}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$3.4\times 10^{4}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">${\mathrm{ V}}_{\mathrm{ D}}\,\,=\,\,-0.05$ </tex-math></inline-formula> V and −0.5 V, respectively. The Si nFinFET presents an <inline-formula> <tex-math notation="LaTeX">${\mathrm{ I}}_{\mathrm{ ON}}$ </tex-math></inline-formula> of <inline-formula> <tex-math notation="LaTeX">$60.4 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">${\mathrm{ V}}_{\mathrm{ D}}\,\,=$ </tex-math></inline-formula> VG-VTH = 0.5 V and shows <inline-formula> <tex-math notation="LaTeX">${\mathrm{ SS}}_{\min }$ </tex-math></inline-formula> of 91, 101 mV/dec, and ION/IOFF of <inline-formula> <tex-math notation="LaTeX">$9.01\times10\,\,^{\mathrm{ 4}}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$5.62\times 10^{5}$ </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">${\mathrm{ V}}_{\mathrm{ D}}\,\,=$ </tex-math></inline-formula> 0.05 V and 0.5 V, respectively. The proposed CFET can simplify the process and shows promising potential for extending scaling beyond the technology node.https://ieeexplore.ieee.org/document/10233696/Self-alignedGe nanowire (NW)Si FinFETcomplementary FET (CFET)single gate |
| spellingShingle | Yi-Wen Lin Shan-Wen Lin Bo-An Chen Chong-Jhe Sun Siao-Cheng Yan Guang-Li Luo Yung-Chun Wu Fu-Ju Hou 3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET IEEE Journal of the Electron Devices Society Self-aligned Ge nanowire (NW) Si FinFET complementary FET (CFET) single gate |
| title | 3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET |
| title_full | 3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET |
| title_fullStr | 3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET |
| title_full_unstemmed | 3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET |
| title_short | 3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET |
| title_sort | 3 d self aligned stacked ge nanowire pgaafet on si nfinfet of single gate cfet |
| topic | Self-aligned Ge nanowire (NW) Si FinFET complementary FET (CFET) single gate |
| url | https://ieeexplore.ieee.org/document/10233696/ |
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