A Three-Dimensional DRAM Using Floating Body Capacitance Cells in an FD-SOI Process

A Three-Dimensional DRAM Using Floating Body Capacitance Cells in an FD-SOI Process

This paper describes a three- dimensional DRAM in which the floating body capacitance (FBC) of a fully depleted SOI (FD-SOI) device is used as a storage node. This 1T DRAM lends itself particularly well to a 3D wafer-to-wafer bonding process because of the absence of deep etched and filled trench ca...

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Bibliographic Details
Main Authors: Xuelian Liu, Aamir Zia
Format: Article
Language:English
Published: Spolecnost pro radioelektronicke inzenyrstvi 2013-12-01
Series:Radioengineering
Subjects:
Capacitor-less 1T DRAM
embedded DRAM
FD-SOI
floating body cell
memory stack
3-D integration
Online Access:http://www.radioeng.cz/fulltexts/2013/13_04_0975_0984.pdf

Internet

http://www.radioeng.cz/fulltexts/2013/13_04_0975_0984.pdf

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