Efficient and Scalable Architecture for Multiple-Chip Implementation of Simulated Bifurcation Machines

Efficient and Scalable Architecture for Multiple-Chip Implementation of Simulated Bifurcation Machines

Ising machines are specialized computers for finding the lowest energy states of Ising spin models, onto which many practical combinatorial optimization problems can be mapped. Simulated bifurcation (SB) is a quantum-inspired parallelizable algorithm for Ising problems that enables scalable multi-ch...

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Bibliographic Details
Main Authors: Tomoya Kashimata, Masaya Yamasaki, Ryo Hidaka, Kosuke Tatsumura
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
Cluster computing
combinatorial optimization
FPGA
hardware acceleration
Ising machine
parallel processing
Online Access:https://ieeexplore.ieee.org/document/10460551/

Internet

https://ieeexplore.ieee.org/document/10460551/

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