A New Technology for Reducing Power Consumption in Synchronous Digital Design Using Tri-State Buffer
This research paper deals with design and implementation of low power 8-bit arithmetic logic units. The main part of power consumption is consumed in ALU in any processor. Therefore, reducing power dissipation in ALU should be requiring. The proposed technique disabled one of the main block of ALU...
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| Format: | Article |
| Language: | English |
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University of Diyala
2018-06-01
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| Series: | Diyala Journal of Engineering Sciences |
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| Online Access: | https://djes.info/index.php/djes/article/view/154 |