A New Technology for Reducing Power Consumption in Synchronous Digital Design Using Tri-State Buffer
This research paper deals with design and implementation of low power 8-bit arithmetic logic units. The main part of power consumption is consumed in ALU in any processor. Therefore, reducing power dissipation in ALU should be requiring. The proposed technique disabled one of the main block of ALU...
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| Format: | Article |
| Language: | English |
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University of Diyala
2018-06-01
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| Series: | Diyala Journal of Engineering Sciences |
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| Online Access: | https://djes.info/index.php/djes/article/view/154 |
| Summary: | This research paper deals with design and implementation of low power 8-bit arithmetic logic units. The main part of power consumption is consumed in ALU in any processor. Therefore, reducing power dissipation in ALU should be requiring. The proposed technique disabled one of the main block of ALU using tri-state logic which is not necessary to use, except the required
processes. In this work, the suggested design is realized by using ASIC methodologies. In order to implement the arithmetic and logic architectures, 130 nm standard cell libraries are used for ASIC execution. The architecture of the design has been created using Verilog HDL language. In addition, it is simulated using ModelSim-Altera 10.3c (Quartus II 14.1) tools. By using tri-state technique, dynamic power and total power are decreased
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| ISSN: | 1999-8716 2616-6909 |