Optimal Test Clock Frequency Based Test Option Generation for Small Delay Defects
Small delay defects (SDD) based test escapes are caused by the nature of transition delay fault (TDF) ATPG, which propagates the fault effect along the shorter path in the interest of run time. However, owing to the benefits of a lesser pattern count and complexity, TDF ATPG is the most feasible opt...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2023-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10268933/ |