Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers
Double silicon drift layers are used to reduce the specific on-resistance (Ron,sp) for a trench-gate-integrated lateral double-diffused MOSFET (DDL TG LDMOS) based on SOI technology in this paper. A trench-gate is incorporated into the oxide trench, a n-type drift layer with a high doping concentrat...
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| Format: | Article |
| Language: | English |
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Elsevier
2020-12-01
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| Series: | Results in Physics |
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| Online Access: | http://www.sciencedirect.com/science/article/pii/S2211379720320295 |
| _version_ | 1818565400974065664 |
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| author | Yuan Wang Shengdong Hu Chang Liu Jian'an Wang Han Yang Shenglong Ran Jie Jiang Gang Guo |
| author_facet | Yuan Wang Shengdong Hu Chang Liu Jian'an Wang Han Yang Shenglong Ran Jie Jiang Gang Guo |
| author_sort | Yuan Wang |
| collection | DOAJ |
| description | Double silicon drift layers are used to reduce the specific on-resistance (Ron,sp) for a trench-gate-integrated lateral double-diffused MOSFET (DDL TG LDMOS) based on SOI technology in this paper. A trench-gate is incorporated into the oxide trench, a n-type drift layer with a high doping concentration is introduced on the topside of the original drift layer around the oxide trench, and a p-type pillar layer with a high doping concentration is inserted between the dual drift layers. First, the incorporated trench-gate constitutes dual current conduction channels, which decreases the Ron,sp. Second, the whole electric fields on the device surface and around the oxide trench are modulated on the basis of RESURF condition, leading to a higher breakdown voltage (BV) at off-state. Finally, the doping concentration of the drift layers is increased by an assistant depletion effect from the p-pillar, which not only improves the BV but also reduces the Ron,sp. Consequently, compared with those of the conventional trench SOI LDMOS on the same drift region of 18 μm and top silicon layer of 25 μm, a higher BV of 477 V and a lower Ron,sp of 32.1 mΩ∙cm2 are obtained for the DDL TG SOI LDMOS, while BV is improved by 33.5% and Ron,sp is reduced by 92.9%, respectively. |
| first_indexed | 2024-12-14T01:40:50Z |
| format | Article |
| id | doaj.art-3b16dd3d5a2549afba4948c2c3d82be3 |
| institution | Directory Open Access Journal |
| issn | 2211-3797 |
| language | English |
| last_indexed | 2024-12-14T01:40:50Z |
| publishDate | 2020-12-01 |
| publisher | Elsevier |
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| series | Results in Physics |
| spelling | doaj.art-3b16dd3d5a2549afba4948c2c3d82be32022-12-21T23:21:44ZengElsevierResults in Physics2211-37972020-12-0119103589Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layersYuan Wang0Shengdong Hu1Chang Liu2Jian'an Wang3Han Yang4Shenglong Ran5Jie Jiang6Gang Guo7Chongqing Engineering Laboratory of High Performance Integrated Circuits, School of Microelectronics and Communication Engineering, Chongqing University, Chongqing 400044, ChinaChongqing Engineering Laboratory of High Performance Integrated Circuits, School of Microelectronics and Communication Engineering, Chongqing University, Chongqing 400044, China; Corresponding author.Chongqing Engineering Laboratory of High Performance Integrated Circuits, School of Microelectronics and Communication Engineering, Chongqing University, Chongqing 400044, ChinaThe National Laboratory of Analogue Integrated Circuits, No. 24 Research Institute of China Electronics Technology Group Corporation, Chongqing 400060, ChinaChongqing Engineering Laboratory of High Performance Integrated Circuits, School of Microelectronics and Communication Engineering, Chongqing University, Chongqing 400044, ChinaChongqing Engineering Laboratory of High Performance Integrated Circuits, School of Microelectronics and Communication Engineering, Chongqing University, Chongqing 400044, ChinaChongqing Engineering Laboratory of High Performance Integrated Circuits, School of Microelectronics and Communication Engineering, Chongqing University, Chongqing 400044, ChinaChina Institute of Atomic Energy, Beijing 102413, ChinaDouble silicon drift layers are used to reduce the specific on-resistance (Ron,sp) for a trench-gate-integrated lateral double-diffused MOSFET (DDL TG LDMOS) based on SOI technology in this paper. A trench-gate is incorporated into the oxide trench, a n-type drift layer with a high doping concentration is introduced on the topside of the original drift layer around the oxide trench, and a p-type pillar layer with a high doping concentration is inserted between the dual drift layers. First, the incorporated trench-gate constitutes dual current conduction channels, which decreases the Ron,sp. Second, the whole electric fields on the device surface and around the oxide trench are modulated on the basis of RESURF condition, leading to a higher breakdown voltage (BV) at off-state. Finally, the doping concentration of the drift layers is increased by an assistant depletion effect from the p-pillar, which not only improves the BV but also reduces the Ron,sp. Consequently, compared with those of the conventional trench SOI LDMOS on the same drift region of 18 μm and top silicon layer of 25 μm, a higher BV of 477 V and a lower Ron,sp of 32.1 mΩ∙cm2 are obtained for the DDL TG SOI LDMOS, while BV is improved by 33.5% and Ron,sp is reduced by 92.9%, respectively.http://www.sciencedirect.com/science/article/pii/S2211379720320295LDMOSDouble silicon drift layersBreakdown voltageSpecific on-resistance |
| spellingShingle | Yuan Wang Shengdong Hu Chang Liu Jian'an Wang Han Yang Shenglong Ran Jie Jiang Gang Guo Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers Results in Physics LDMOS Double silicon drift layers Breakdown voltage Specific on-resistance |
| title | Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers |
| title_full | Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers |
| title_fullStr | Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers |
| title_full_unstemmed | Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers |
| title_short | Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers |
| title_sort | reducing the specific on resistance for a trench gate integrated soi ldmos by using the double silicon drift layers |
| topic | LDMOS Double silicon drift layers Breakdown voltage Specific on-resistance |
| url | http://www.sciencedirect.com/science/article/pii/S2211379720320295 |
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