Single-Path High-Resolution Digital PWM Architectures With Cascadability of Delay Lines

Single-Path High-Resolution Digital PWM Architectures With Cascadability of Delay Lines

This paper introduces two new single-path and cascaded High-Resolution Digital Pulse Width Modulation (HRDPWM) architectures. The proposed single-path architecture uses fewer FPGA resources to achieve the same resolution as conventional dual-path architectures. Moreover, the generated HRDPWM signal...

Full description

Bibliographic Details
Main Authors: Marziyeh Hajiheidari, Joel Fushekati, Mohammad Emad, Bas J. D. Vermulst, Jeroen van Duivenbode, Henk Huisman
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Open Journal of Power Electronics
Subjects:
Digital pulse width modulation (DPWM)
delay line
high resolution (HR)
high switching frequency
Online Access:https://ieeexplore.ieee.org/document/10806584/

Internet

https://ieeexplore.ieee.org/document/10806584/

Similar Items