Novel Ternary Logic Gates Design in Nanoelectronics
In this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is reduced considerably. In addition, ST-OR and S...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
VSB-Technical University of Ostrava
2019-01-01
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| Series: | Advances in Electrical and Electronic Engineering |
| Subjects: | |
| Online Access: | http://advances.utc.sk/index.php/AEEE/article/view/3156 |