Novel Ternary Logic Gates Design in Nanoelectronics
In this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is reduced considerably. In addition, ST-OR and S...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
VSB-Technical University of Ostrava
2019-01-01
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| Series: | Advances in Electrical and Electronic Engineering |
| Subjects: | |
| Online Access: | http://advances.utc.sk/index.php/AEEE/article/view/3156 |
| _version_ | 1797826958863630336 |
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| author | Sajjad Etezadi Seied Ali Hosseini |
| author_facet | Sajjad Etezadi Seied Ali Hosseini |
| author_sort | Sajjad Etezadi |
| collection | DOAJ |
| description | In this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is reduced considerably. In addition, ST-OR and ST-AND are generated directly instead of ST-NAND and ST-NOR. The proposed gates have a high noise margin near V_(DD)/4. The simulation results indicated that the power consumption and PDP underwent a~sharp decrease and noise margin showed a considerable increase in comparison to both one supply and two supply based designs in previous works. PDP is improved in the proposed OR, as compared to one supply and two supply based previous works about 83% and 63%, respectively. Also, a memory cell is designed using the proposed STI logic gate, which has a considerably lower static power to store logic ‘1’ and the static noise margin, as compared to other designs. |
| first_indexed | 2024-04-09T12:40:34Z |
| format | Article |
| id | doaj.art-3daa59ff8b054daa88541e0f15a532c2 |
| institution | Directory Open Access Journal |
| issn | 1336-1376 1804-3119 |
| language | English |
| last_indexed | 2024-04-09T12:40:34Z |
| publishDate | 2019-01-01 |
| publisher | VSB-Technical University of Ostrava |
| record_format | Article |
| series | Advances in Electrical and Electronic Engineering |
| spelling | doaj.art-3daa59ff8b054daa88541e0f15a532c22023-05-14T20:50:13ZengVSB-Technical University of OstravaAdvances in Electrical and Electronic Engineering1336-13761804-31192019-01-0117329430510.15598/aeee.v17i3.31561056Novel Ternary Logic Gates Design in NanoelectronicsSajjad Etezadi0Seied Ali Hosseini1Department of Electronic, College of Electrical Engineering, Bandar Abbas Branch, Islamic Azad University, Bandar Abbas, IranDepartment of Electronic, College of Electrical Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, IranIn this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is reduced considerably. In addition, ST-OR and ST-AND are generated directly instead of ST-NAND and ST-NOR. The proposed gates have a high noise margin near V_(DD)/4. The simulation results indicated that the power consumption and PDP underwent a~sharp decrease and noise margin showed a considerable increase in comparison to both one supply and two supply based designs in previous works. PDP is improved in the proposed OR, as compared to one supply and two supply based previous works about 83% and 63%, respectively. Also, a memory cell is designed using the proposed STI logic gate, which has a considerably lower static power to store logic ‘1’ and the static noise margin, as compared to other designs.http://advances.utc.sk/index.php/AEEE/article/view/3156cntfetsdouble supply voltagesstatic power reductionternary logic gatesternary memory cell. |
| spellingShingle | Sajjad Etezadi Seied Ali Hosseini Novel Ternary Logic Gates Design in Nanoelectronics Advances in Electrical and Electronic Engineering cntfets double supply voltages static power reduction ternary logic gates ternary memory cell. |
| title | Novel Ternary Logic Gates Design in Nanoelectronics |
| title_full | Novel Ternary Logic Gates Design in Nanoelectronics |
| title_fullStr | Novel Ternary Logic Gates Design in Nanoelectronics |
| title_full_unstemmed | Novel Ternary Logic Gates Design in Nanoelectronics |
| title_short | Novel Ternary Logic Gates Design in Nanoelectronics |
| title_sort | novel ternary logic gates design in nanoelectronics |
| topic | cntfets double supply voltages static power reduction ternary logic gates ternary memory cell. |
| url | http://advances.utc.sk/index.php/AEEE/article/view/3156 |
| work_keys_str_mv | AT sajjadetezadi novelternarylogicgatesdesigninnanoelectronics AT seiedalihosseini novelternarylogicgatesdesigninnanoelectronics |