Novel Ternary Logic Gates Design in Nanoelectronics

Novel Ternary Logic Gates Design in Nanoelectronics

In this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is reduced considerably. In addition, ST-OR and S...

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Bibliographic Details
Main Authors:	Sajjad Etezadi, Seied Ali Hosseini
Format:	Article
Language:	English
Published:	VSB-Technical University of Ostrava 2019-01-01
Series:	Advances in Electrical and Electronic Engineering
Subjects:	cntfets double supply voltages static power reduction ternary logic gates ternary memory cell.
Online Access:	http://advances.utc.sk/index.php/AEEE/article/view/3156

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