Design and Emulation of All-Digital Phase-Locked Loop on FPGA

Design and Emulation of All-Digital Phase-Locked Loop on FPGA

This paper demonstrates the design and implementation of an all-digital phase-locked<br />loop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation technique<br />to show the feasibility and effectiveness of the ADPLL in the early design stage. A D-S modulator<...

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Bibliographic Details
Main Authors: Saichandrateja Radhapuram, Takuya Yoshihara, Toshimasa Matsuoka
Format: Article
Language:English
Published: MDPI AG 2019-11-01
Series:Electronics
Subjects:
all-digital phase-locked loop
digitally controlled oscillator
fpga
Online Access:https://www.mdpi.com/2079-9292/8/11/1307

Internet

https://www.mdpi.com/2079-9292/8/11/1307

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