FPGA’s Dual-Port ROM-Based 8x8 Multiplier for Area Optimized Implementation of DSP Systems
FPGA’s block memory may be programmed as a single or dual-port RAM/ROM module that leads to an area-efficient implementation of memory-based systems. In this contest, various works of carrying out an optimized implementation of simple to complex DSP systems on embedded building blocks may be seen. T...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Iran University of Science and Technology
2021-12-01
|
| Series: | Iranian Journal of Electrical and Electronic Engineering |
| Subjects: | |
| Online Access: | http://ijeee.iust.ac.ir/article-1-2011-en.html |