FPGA’s Dual-Port ROM-Based 8x8 Multiplier for Area Optimized Implementation of DSP Systems
FPGA’s block memory may be programmed as a single or dual-port RAM/ROM module that leads to an area-efficient implementation of memory-based systems. In this contest, various works of carrying out an optimized implementation of simple to complex DSP systems on embedded building blocks may be seen. T...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Iran University of Science and Technology
2021-12-01
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| Series: | Iranian Journal of Electrical and Electronic Engineering |
| Subjects: | |
| Online Access: | http://ijeee.iust.ac.ir/article-1-2011-en.html |
| _version_ | 1818620591411822592 |
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| author | A. Pathan T. Memon |
| author_facet | A. Pathan T. Memon |
| author_sort | A. Pathan |
| collection | DOAJ |
| description | FPGA’s block memory may be programmed as a single or dual-port RAM/ROM module that leads to an area-efficient implementation of memory-based systems. In this contest, various works of carrying out an optimized implementation of simple to complex DSP systems on embedded building blocks may be seen. The multiplier is a core element of the DSP systems, and in implementing a memory-based multiplier, it is observed that one of the operands is kept constant, hence leading the design to a constant-coefficient multiplication. This paper shows Virtex-7 FPGA’s dual-port ROM-based implementation of an 8x8 variable-coefficient multiplier that may be used in several simple to complex DSP applications. The novelty of the proposed design is to configure the block ROM in dual-port mode and, hence, get four partial products in two clock cycles and introduce two unconventional adder approaches for partial product addition. This approach leads to fully resource utilization and the provision of a variable-coefficient multiplier. The work also shows the comparison of proposed architecture with already existing memory-based implementations and concludes the work as a novel step towards the efficient memory-based implementation of multiplier core. |
| first_indexed | 2024-12-16T17:55:49Z |
| format | Article |
| id | doaj.art-3f6aecb926ab4977b489eb68b9487759 |
| institution | Directory Open Access Journal |
| issn | 1735-2827 2383-3890 |
| language | English |
| last_indexed | 2024-12-16T17:55:49Z |
| publishDate | 2021-12-01 |
| publisher | Iran University of Science and Technology |
| record_format | Article |
| series | Iranian Journal of Electrical and Electronic Engineering |
| spelling | doaj.art-3f6aecb926ab4977b489eb68b94877592022-12-21T22:22:10ZengIran University of Science and TechnologyIranian Journal of Electrical and Electronic Engineering1735-28272383-38902021-12-0117420112011FPGA’s Dual-Port ROM-Based 8x8 Multiplier for Area Optimized Implementation of DSP SystemsA. Pathan0T. Memon1 School of Information Technology and Engineering, Melbourne Institute of Technology, Melbourne, Australia. School of Information Technology and Engineering, Melbourne Institute of Technology, Melbourne, Australia and Department of Electronic Engineering, Mehran University of Engineering and Technology, Jamshoro, Pakistan. FPGA’s block memory may be programmed as a single or dual-port RAM/ROM module that leads to an area-efficient implementation of memory-based systems. In this contest, various works of carrying out an optimized implementation of simple to complex DSP systems on embedded building blocks may be seen. The multiplier is a core element of the DSP systems, and in implementing a memory-based multiplier, it is observed that one of the operands is kept constant, hence leading the design to a constant-coefficient multiplication. This paper shows Virtex-7 FPGA’s dual-port ROM-based implementation of an 8x8 variable-coefficient multiplier that may be used in several simple to complex DSP applications. The novelty of the proposed design is to configure the block ROM in dual-port mode and, hence, get four partial products in two clock cycles and introduce two unconventional adder approaches for partial product addition. This approach leads to fully resource utilization and the provision of a variable-coefficient multiplier. The work also shows the comparison of proposed architecture with already existing memory-based implementations and concludes the work as a novel step towards the efficient memory-based implementation of multiplier core.http://ijeee.iust.ac.ir/article-1-2011-en.htmlblock memorydigital signal processingfpgamultiplier |
| spellingShingle | A. Pathan T. Memon FPGA’s Dual-Port ROM-Based 8x8 Multiplier for Area Optimized Implementation of DSP Systems Iranian Journal of Electrical and Electronic Engineering block memory digital signal processing fpga multiplier |
| title | FPGA’s Dual-Port ROM-Based 8x8 Multiplier for Area Optimized Implementation of DSP Systems |
| title_full | FPGA’s Dual-Port ROM-Based 8x8 Multiplier for Area Optimized Implementation of DSP Systems |
| title_fullStr | FPGA’s Dual-Port ROM-Based 8x8 Multiplier for Area Optimized Implementation of DSP Systems |
| title_full_unstemmed | FPGA’s Dual-Port ROM-Based 8x8 Multiplier for Area Optimized Implementation of DSP Systems |
| title_short | FPGA’s Dual-Port ROM-Based 8x8 Multiplier for Area Optimized Implementation of DSP Systems |
| title_sort | fpga s dual port rom based 8x8 multiplier for area optimized implementation of dsp systems |
| topic | block memory digital signal processing fpga multiplier |
| url | http://ijeee.iust.ac.ir/article-1-2011-en.html |
| work_keys_str_mv | AT apathan fpgasdualportrombased8x8multiplierforareaoptimizedimplementationofdspsystems AT tmemon fpgasdualportrombased8x8multiplierforareaoptimizedimplementationofdspsystems |