| Summary: | We report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully very large-scale integration (VLSI)-compatible flow. Scaling of the equivalent oxide thickness EOT in conjunction with high-κ dielectric engineering improves the device performance; with an optimized gate stack having an EOT of 1.0 nm, the sub-threshold swing S is 76.8 mV/dec., and the peak transconductance gm is 1.65 mS/μm, at V<sub>ds</sub> of 0.5 V, for a gate-all-around nanowire MOSFET having a gate length L<sub>g</sub> of 90 nm, a nanowire height H<sub>NW</sub> of 25 nm, and a nanowire width W<sub>NW</sub> of 20 nm, resulting in Q ≡ gm/S = 21.5, a record for InAs on silicon. Furthermore, we report a source/drain resistance R<sub>sd</sub> of 160-200 Ω·μm, amongst the lowest values reported for III-V MOSFETs. Our VLSI-compatible process provides high device yield, which enables statistically reliable extraction of electron transport parameters, such as unidirectional thermal velocity vtx of 3-4×10<sup>7</sup> cm/s and back-scattering coefficient r<sub>c</sub> as a function of gate length.
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