High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates
We report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully very large-scale integration (VLSI)-compatible flow. Scaling of the equivalent oxide thickness EOT in conjunction with high-κ dielectric engineering improves the dev...
| Main Authors: | , , , , , , , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2016-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/7488198/ |
| _version_ | 1819162781059907584 |
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| author | Gerben Doornbos Martin Holland Georgios Vellianitis Mark J. H. Van Dal Blandine Duriez Richard Oxland Aryan Afzalian Ta-Kun Chen Gordon Hsieh Matthias Passlack Yee-Chia Yeo |
| author_facet | Gerben Doornbos Martin Holland Georgios Vellianitis Mark J. H. Van Dal Blandine Duriez Richard Oxland Aryan Afzalian Ta-Kun Chen Gordon Hsieh Matthias Passlack Yee-Chia Yeo |
| author_sort | Gerben Doornbos |
| collection | DOAJ |
| description | We report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully very large-scale integration (VLSI)-compatible flow. Scaling of the equivalent oxide thickness EOT in conjunction with high-κ dielectric engineering improves the device performance; with an optimized gate stack having an EOT of 1.0 nm, the sub-threshold swing S is 76.8 mV/dec., and the peak transconductance gm is 1.65 mS/μm, at V<sub>ds</sub> of 0.5 V, for a gate-all-around nanowire MOSFET having a gate length L<sub>g</sub> of 90 nm, a nanowire height H<sub>NW</sub> of 25 nm, and a nanowire width W<sub>NW</sub> of 20 nm, resulting in Q ≡ gm/S = 21.5, a record for InAs on silicon. Furthermore, we report a source/drain resistance R<sub>sd</sub> of 160-200 Ω·μm, amongst the lowest values reported for III-V MOSFETs. Our VLSI-compatible process provides high device yield, which enables statistically reliable extraction of electron transport parameters, such as unidirectional thermal velocity vtx of 3-4×10<sup>7</sup> cm/s and back-scattering coefficient r<sub>c</sub> as a function of gate length. |
| first_indexed | 2024-12-22T17:33:41Z |
| format | Article |
| id | doaj.art-3f9a947ff28244ed8ba1c54803efcb7e |
| institution | Directory Open Access Journal |
| issn | 2168-6734 |
| language | English |
| last_indexed | 2024-12-22T17:33:41Z |
| publishDate | 2016-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj.art-3f9a947ff28244ed8ba1c54803efcb7e2022-12-21T18:18:33ZengIEEEIEEE Journal of the Electron Devices Society2168-67342016-01-014525325910.1109/JEDS.2016.25742037488198High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si SubstratesGerben Doornbos0https://orcid.org/0000-0002-6259-0021Martin Holland1Georgios Vellianitis2Mark J. H. Van Dal3Blandine Duriez4Richard Oxland5Aryan Afzalian6Ta-Kun Chen7Gordon Hsieh8Matthias Passlack9Yee-Chia Yeo10TSMC R&D Europe B.V., Leuven, BelgiumTSMC R&D Europe B.V., Leuven, BelgiumTSMC R&D Europe B.V., Leuven, BelgiumTSMC R&D Europe B.V., Leuven, BelgiumTSMC R&D Europe B.V., Leuven, BelgiumTSMC R&D Europe B.V., Leuven, BelgiumTSMC R&D Europe B.V., Leuven, BelgiumTaiwan Semiconductor Manufacturing Company, Hsinchu, TaiwanTaiwan Semiconductor Manufacturing Company, Hsinchu, TaiwanTSMC R&D Europe B.V., Leuven, BelgiumTaiwan Semiconductor Manufacturing Company, Hsinchu, TaiwanWe report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully very large-scale integration (VLSI)-compatible flow. Scaling of the equivalent oxide thickness EOT in conjunction with high-κ dielectric engineering improves the device performance; with an optimized gate stack having an EOT of 1.0 nm, the sub-threshold swing S is 76.8 mV/dec., and the peak transconductance gm is 1.65 mS/μm, at V<sub>ds</sub> of 0.5 V, for a gate-all-around nanowire MOSFET having a gate length L<sub>g</sub> of 90 nm, a nanowire height H<sub>NW</sub> of 25 nm, and a nanowire width W<sub>NW</sub> of 20 nm, resulting in Q ≡ gm/S = 21.5, a record for InAs on silicon. Furthermore, we report a source/drain resistance R<sub>sd</sub> of 160-200 Ω·μm, amongst the lowest values reported for III-V MOSFETs. Our VLSI-compatible process provides high device yield, which enables statistically reliable extraction of electron transport parameters, such as unidirectional thermal velocity vtx of 3-4×10<sup>7</sup> cm/s and back-scattering coefficient r<sub>c</sub> as a function of gate length.https://ieeexplore.ieee.org/document/7488198/High-mobility channelMOSFETnanowiresIII-V semiconductor materials |
| spellingShingle | Gerben Doornbos Martin Holland Georgios Vellianitis Mark J. H. Van Dal Blandine Duriez Richard Oxland Aryan Afzalian Ta-Kun Chen Gordon Hsieh Matthias Passlack Yee-Chia Yeo High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates IEEE Journal of the Electron Devices Society High-mobility channel MOSFET nanowires III-V semiconductor materials |
| title | High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates |
| title_full | High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates |
| title_fullStr | High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates |
| title_full_unstemmed | High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates |
| title_short | High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates |
| title_sort | high performance inas gate all around nanowire mosfets on 300 mm si substrates |
| topic | High-mobility channel MOSFET nanowires III-V semiconductor materials |
| url | https://ieeexplore.ieee.org/document/7488198/ |
| work_keys_str_mv | AT gerbendoornbos highperformanceinasgateallaroundnanowiremosfetson300mmsisubstrates AT martinholland highperformanceinasgateallaroundnanowiremosfetson300mmsisubstrates AT georgiosvellianitis highperformanceinasgateallaroundnanowiremosfetson300mmsisubstrates AT markjhvandal highperformanceinasgateallaroundnanowiremosfetson300mmsisubstrates AT blandineduriez highperformanceinasgateallaroundnanowiremosfetson300mmsisubstrates AT richardoxland highperformanceinasgateallaroundnanowiremosfetson300mmsisubstrates AT aryanafzalian highperformanceinasgateallaroundnanowiremosfetson300mmsisubstrates AT takunchen highperformanceinasgateallaroundnanowiremosfetson300mmsisubstrates AT gordonhsieh highperformanceinasgateallaroundnanowiremosfetson300mmsisubstrates AT matthiaspasslack highperformanceinasgateallaroundnanowiremosfetson300mmsisubstrates AT yeechiayeo highperformanceinasgateallaroundnanowiremosfetson300mmsisubstrates |