DC‐offset elimination method for grid synchronisation

For three‐phase power system, the synchronous reference frame (SRF) phase‐locked loop (PLL) is probably the most widely used synchronisation technique under ideal grid condition. However, the presence of dc‐offset causes fundamental frequency oscillations errors in estimated phase. To deal with this...

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Bibliographic Details
Main Authors: Yunlu Li, Dazhi Wang, Yi Ning, Nanmu Hui
Format: Article
Language:English
Published: Wiley 2017-03-01
Series:Electronics Letters
Subjects:
Online Access:https://doi.org/10.1049/el.2016.4570