Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits
Three-dimensional (3-D) integration offers a promising solution to the technology scaling barriers. Reliability of the 3-D Integrated Circuits (ICs) is highly dependent on the integrity of the underlying interconnect. Through Silicon Via (TSV) based 3-D ICs would suffer from low yield due to the fau...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2020-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/8832259/ |
| _version_ | 1818664031649529856 |
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| author | Muhammad Imran Hyunseung Han Jooho Kim Taehyun Kwon Jaeyong Chung Joon-Sung Yang |
| author_facet | Muhammad Imran Hyunseung Han Jooho Kim Taehyun Kwon Jaeyong Chung Joon-Sung Yang |
| author_sort | Muhammad Imran |
| collection | DOAJ |
| description | Three-dimensional (3-D) integration offers a promising solution to the technology scaling barriers. Reliability of the 3-D Integrated Circuits (ICs) is highly dependent on the integrity of the underlying interconnect. Through Silicon Via (TSV) based 3-D ICs would suffer from low yield due to the faults in TSVs. In addition, TSVs introduce stress and noise in the substrate. Adding redundant TSVs for repairing the faulty ones has commonly been proposed to improve the yield of TSV-based 3-D ICs. The existing TSV repair approaches employ a number of spare TSVs in a group of signal TSVs. We propose a TSV virtualization based repair architecture which utilizes a single redundant TSV to repair multiple faulty TSVs. The proposed architecture relies on transmitting multiple bits through a single TSV using multi-level voltage quantization. It makes efficient use of the TSV redundancies in repairing the faulty TSVs. With less number of spare TSVs, the proposed architecture can reduce the area overhead by more than 70%. Reduction in the TSV count allows greater interconnect density and helps to mitigate the TSV-induced noise and stresses. Alternatively, for a similar number of spare TSVs, the proposed method can enhance the fault tolerance capability of the conventional approaches thus leading to an enhanced chip yield. The eye diagram simulations using an electrical model of the TSV show a reduction of less than 5% in noise margin when using a 16-level voltage quantization at a data rate of 5 Gbps which is typical for 3-D integration applications. |
| first_indexed | 2024-12-17T05:26:17Z |
| format | Article |
| id | doaj.art-410307af04b249fe8d00d93780f3bce7 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-17T05:26:17Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-410307af04b249fe8d00d93780f3bce72022-12-21T22:01:51ZengIEEEIEEE Access2169-35362020-01-018422314224210.1109/ACCESS.2019.29402118832259Virtualization-Based Efficient TSV Repair for 3-D Integrated CircuitsMuhammad Imran0Hyunseung Han1Jooho Kim2Taehyun Kwon3Jaeyong Chung4https://orcid.org/0000-0001-5819-1995Joon-Sung Yang5https://orcid.org/0000-0002-1502-5353Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaMemory Division, Samsung Electronics, Hwaseong, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electronics Engineering, Incheon National University, Incheon, South KoreaDepartment of Systems Semiconductor Engineering, Yonsei University, Seoul, South KoreaThree-dimensional (3-D) integration offers a promising solution to the technology scaling barriers. Reliability of the 3-D Integrated Circuits (ICs) is highly dependent on the integrity of the underlying interconnect. Through Silicon Via (TSV) based 3-D ICs would suffer from low yield due to the faults in TSVs. In addition, TSVs introduce stress and noise in the substrate. Adding redundant TSVs for repairing the faulty ones has commonly been proposed to improve the yield of TSV-based 3-D ICs. The existing TSV repair approaches employ a number of spare TSVs in a group of signal TSVs. We propose a TSV virtualization based repair architecture which utilizes a single redundant TSV to repair multiple faulty TSVs. The proposed architecture relies on transmitting multiple bits through a single TSV using multi-level voltage quantization. It makes efficient use of the TSV redundancies in repairing the faulty TSVs. With less number of spare TSVs, the proposed architecture can reduce the area overhead by more than 70%. Reduction in the TSV count allows greater interconnect density and helps to mitigate the TSV-induced noise and stresses. Alternatively, for a similar number of spare TSVs, the proposed method can enhance the fault tolerance capability of the conventional approaches thus leading to an enhanced chip yield. The eye diagram simulations using an electrical model of the TSV show a reduction of less than 5% in noise margin when using a 16-level voltage quantization at a data rate of 5 Gbps which is typical for 3-D integration applications.https://ieeexplore.ieee.org/document/8832259/3-D integrated circuiteye diagram simulationsmultiple bits transmissionthrough silicon via (TSV)TSV VirtualizationTSV repair |
| spellingShingle | Muhammad Imran Hyunseung Han Jooho Kim Taehyun Kwon Jaeyong Chung Joon-Sung Yang Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits IEEE Access 3-D integrated circuit eye diagram simulations multiple bits transmission through silicon via (TSV) TSV Virtualization TSV repair |
| title | Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits |
| title_full | Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits |
| title_fullStr | Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits |
| title_full_unstemmed | Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits |
| title_short | Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits |
| title_sort | virtualization based efficient tsv repair for 3 d integrated circuits |
| topic | 3-D integrated circuit eye diagram simulations multiple bits transmission through silicon via (TSV) TSV Virtualization TSV repair |
| url | https://ieeexplore.ieee.org/document/8832259/ |
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