High Power and High Frequency CMOS Oscillator With Source-to-Drain Coupling and Capacitive Load Reduction Circuit
A design for a high-output-power, high-frequency CMOS oscillator is presented in this paper. The proposed oscillator can increase the output power by coupling the signal at the source of the core transistor to the drain of the buffer transistor. In addition, the source-to-drain coupling generates an...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2020-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9149578/ |