Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications
A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including nine...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2023-12-01
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| Series: | Sensors |
| Subjects: | |
| Online Access: | https://www.mdpi.com/1424-8220/23/24/9644 |
| _version_ | 1797379415878926336 |
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| author | Christoph Ribisch Michael Hofbauer Seyed Saman Kohneh Poushi Alexander Zimmer Kerstin Schneider-Hornstein Bernhard Goll Horst Zimmermann |
| author_facet | Christoph Ribisch Michael Hofbauer Seyed Saman Kohneh Poushi Alexander Zimmer Kerstin Schneider-Hornstein Bernhard Goll Horst Zimmermann |
| author_sort | Christoph Ribisch |
| collection | DOAJ |
| description | A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including nine SPADs using 0.18 µm high-voltage CMOS technology. The gating circuit achieves rise and fall times of 480 ps and 280 ps, respectively, and a minimum full-width-at-half-maximum pulse width of 1.26 ns. Thanks to a fast and sensitive comparator, a detection threshold for avalanche events of less than 100 mV is possible. The power consumption of all nine channels is about 250 mW in total. This gating chip is used to characterize the integrated SPADs. A photon detection probability of around 50% at 9.9 V excess bias and for a wavelength of 635 nm is found. |
| first_indexed | 2024-03-08T20:22:54Z |
| format | Article |
| id | doaj.art-42c5031092cb465793f33ad647689fa4 |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-03-08T20:22:54Z |
| publishDate | 2023-12-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-42c5031092cb465793f33ad647689fa42023-12-22T14:40:04ZengMDPI AGSensors1424-82202023-12-012324964410.3390/s23249644Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum ApplicationsChristoph Ribisch0Michael Hofbauer1Seyed Saman Kohneh Poushi2Alexander Zimmer3Kerstin Schneider-Hornstein4Bernhard Goll5Horst Zimmermann6Institute of Electrodynamics, Microwave and Circuit Engineering, Faculty of Electrical Engineering and Information Technology, Technische Universität Wien, 1040 Vienna, AustriaInstitute of Electrodynamics, Microwave and Circuit Engineering, Faculty of Electrical Engineering and Information Technology, Technische Universität Wien, 1040 Vienna, AustriaInstitute of Electrodynamics, Microwave and Circuit Engineering, Faculty of Electrical Engineering and Information Technology, Technische Universität Wien, 1040 Vienna, AustriaX-FAB, 99097 Erfurt, GermanyInstitute of Electrodynamics, Microwave and Circuit Engineering, Faculty of Electrical Engineering and Information Technology, Technische Universität Wien, 1040 Vienna, AustriaInstitute of Electrodynamics, Microwave and Circuit Engineering, Faculty of Electrical Engineering and Information Technology, Technische Universität Wien, 1040 Vienna, AustriaInstitute of Electrodynamics, Microwave and Circuit Engineering, Faculty of Electrical Engineering and Information Technology, Technische Universität Wien, 1040 Vienna, AustriaA gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including nine SPADs using 0.18 µm high-voltage CMOS technology. The gating circuit achieves rise and fall times of 480 ps and 280 ps, respectively, and a minimum full-width-at-half-maximum pulse width of 1.26 ns. Thanks to a fast and sensitive comparator, a detection threshold for avalanche events of less than 100 mV is possible. The power consumption of all nine channels is about 250 mW in total. This gating chip is used to characterize the integrated SPADs. A photon detection probability of around 50% at 9.9 V excess bias and for a wavelength of 635 nm is found.https://www.mdpi.com/1424-8220/23/24/9644single-photon avalanche diodeSPADgating circuitCMOSquantum simulator |
| spellingShingle | Christoph Ribisch Michael Hofbauer Seyed Saman Kohneh Poushi Alexander Zimmer Kerstin Schneider-Hornstein Bernhard Goll Horst Zimmermann Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications Sensors single-photon avalanche diode SPAD gating circuit CMOS quantum simulator |
| title | Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications |
| title_full | Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications |
| title_fullStr | Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications |
| title_full_unstemmed | Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications |
| title_short | Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications |
| title_sort | multi channel gating chip in 0 18 µm high voltage cmos for quantum applications |
| topic | single-photon avalanche diode SPAD gating circuit CMOS quantum simulator |
| url | https://www.mdpi.com/1424-8220/23/24/9644 |
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