Low-power design-for-test implementation on phase-locked loop design
Low-power design for test is the need of the hour for any system-on-chip designer. The low-power design techniques have been a major challenge to both the designer as well as the testing engineer. With so many advancements in low-power technology in the phase of register transfer logic design, funct...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
SAGE Publishing
2019-09-01
|
| Series: | Measurement + Control |
| Online Access: | https://doi.org/10.1177/0020294019858089 |