A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-spee...

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Bibliographic Details
Main Authors: Thanikodi Manoj Kumar, Kasarla Satish Reddy, Stefano Rinaldi, Bidare Divakarachari Parameshachari, Kavitha Arunachalam
Format: Article
Language:English
Published: MDPI AG 2021-08-01
Series:Electronics
Subjects:
advanced encryption standard
composite field arithmetic
device security
Look-Up Table
modified positive polarity reed muller
pipeline
Online Access:https://www.mdpi.com/2079-9292/10/16/2023

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https://www.mdpi.com/2079-9292/10/16/2023

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