A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application
Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-spee...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-08-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/16/2023 |
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| author | Thanikodi Manoj Kumar Kasarla Satish Reddy Stefano Rinaldi Bidare Divakarachari Parameshachari Kavitha Arunachalam |
| author_facet | Thanikodi Manoj Kumar Kasarla Satish Reddy Stefano Rinaldi Bidare Divakarachari Parameshachari Kavitha Arunachalam |
| author_sort | Thanikodi Manoj Kumar |
| collection | DOAJ |
| description | Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the Look-Up Table (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD. |
| first_indexed | 2024-03-10T08:51:30Z |
| format | Article |
| id | doaj.art-44618ad0ddb64f0b975d56bc5bca720b |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T08:51:30Z |
| publishDate | 2021-08-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-44618ad0ddb64f0b975d56bc5bca720b2023-11-22T07:26:04ZengMDPI AGElectronics2079-92922021-08-011016202310.3390/electronics10162023A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography ApplicationThanikodi Manoj Kumar0Kasarla Satish Reddy1Stefano Rinaldi2Bidare Divakarachari Parameshachari3Kavitha Arunachalam4Department of Electronics and Communication Engineering, Karpagam Institute of Technology, Coimbatore 641105, IndiaDepartment of Electronics and Communication Engineering, CVR College of Engineering, Hyderabad 501510, IndiaDepartment of Information Engineering, University of Brescia, Via Branze 38, 25123 Brescia, ItalyDepartment of Telecommunication Engineering, GSSS Institute of Engineering and Technology for Women, Mysuru 570016, IndiaDepartment of ECE, M. Kumarasamy College of Engineering, Karur 639113, IndiaNowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the Look-Up Table (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.https://www.mdpi.com/2079-9292/10/16/2023advanced encryption standardcomposite field arithmeticdevice securityLook-Up Tablemodified positive polarity reed mullerpipeline |
| spellingShingle | Thanikodi Manoj Kumar Kasarla Satish Reddy Stefano Rinaldi Bidare Divakarachari Parameshachari Kavitha Arunachalam A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application Electronics advanced encryption standard composite field arithmetic device security Look-Up Table modified positive polarity reed muller pipeline |
| title | A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application |
| title_full | A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application |
| title_fullStr | A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application |
| title_full_unstemmed | A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application |
| title_short | A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application |
| title_sort | low area high speed fpga implementation of aes architecture for cryptography application |
| topic | advanced encryption standard composite field arithmetic device security Look-Up Table modified positive polarity reed muller pipeline |
| url | https://www.mdpi.com/2079-9292/10/16/2023 |
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