Study and design of region of interest encoding algorithm for HEVC based on FPGA

Study and design of region of interest encoding algorithm for HEVC based on FPGA

In order to decrease the bit-rate of video encoding while keeping quality of video, considering the parallel feature of FPGA and block processing feature of HEVC, a block based Gaussian background model-ROI extraction mapping algorithm is proposed and implemented for HEVC video encoder. Firstly, bac...

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Bibliographic Details
Main Authors: Li Shen, Yan Wei, Xia Jun, Cui Zhengdong, Chai Zhilei
Format: Article
Language:zho
Published: National Computer System Engineering Research Institute of China 2018-07-01
Series:Dianzi Jishu Yingyong
Subjects:
ROI extraction
background model building
FPGA
vary-quality video encoding
HEVC
Online Access:http://www.chinaaet.com/article/3000085831

Internet

http://www.chinaaet.com/article/3000085831

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