Fractional register calculation and optimization in scheduling based Latency-Insensitive design
In nano technology design, communication wires are not scaled down similar to logic gates. This will cause appearance of delays in the communication wires. Latency-Insensitive design is a method that separates blocks design from the communication wires design. Fractional Registers are storage elemen...
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| Format: | Article |
| Language: | English |
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Elsevier
2020-02-01
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| Series: | Engineering Science and Technology, an International Journal |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2215098618315465 |