Fractional register calculation and optimization in scheduling based Latency-Insensitive design
In nano technology design, communication wires are not scaled down similar to logic gates. This will cause appearance of delays in the communication wires. Latency-Insensitive design is a method that separates blocks design from the communication wires design. Fractional Registers are storage elemen...
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| Format: | Article |
| Language: | English |
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Elsevier
2020-02-01
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| Series: | Engineering Science and Technology, an International Journal |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2215098618315465 |
| _version_ | 1828422238570807296 |
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| author | Mahdi Zare |
| author_facet | Mahdi Zare |
| author_sort | Mahdi Zare |
| collection | DOAJ |
| description | In nano technology design, communication wires are not scaled down similar to logic gates. This will cause appearance of delays in the communication wires. Latency-Insensitive design is a method that separates blocks design from the communication wires design. Fractional Registers are storage elements that are utilized in the Latency-Insensitive design. This paper attends the area of fractional registers and proposes a simpler structure for them. The proposed structure is described and simulated in several synthetic and real world systems. The simulation results show an average 80.3% reduction in the fractional registers area and 4.6% reduction in the total systems area. Keywords: System on Chip, Digital communication, Synchronous systems, Latency insensitive, Input buffers |
| first_indexed | 2024-12-10T15:44:48Z |
| format | Article |
| id | doaj.art-487af8d5ccdc413593a4e3376025c733 |
| institution | Directory Open Access Journal |
| issn | 2215-0986 |
| language | English |
| last_indexed | 2024-12-10T15:44:48Z |
| publishDate | 2020-02-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Engineering Science and Technology, an International Journal |
| spelling | doaj.art-487af8d5ccdc413593a4e3376025c7332022-12-22T01:43:00ZengElsevierEngineering Science and Technology, an International Journal2215-09862020-02-01231204210Fractional register calculation and optimization in scheduling based Latency-Insensitive designMahdi Zare0Department of Electronic Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, IranIn nano technology design, communication wires are not scaled down similar to logic gates. This will cause appearance of delays in the communication wires. Latency-Insensitive design is a method that separates blocks design from the communication wires design. Fractional Registers are storage elements that are utilized in the Latency-Insensitive design. This paper attends the area of fractional registers and proposes a simpler structure for them. The proposed structure is described and simulated in several synthetic and real world systems. The simulation results show an average 80.3% reduction in the fractional registers area and 4.6% reduction in the total systems area. Keywords: System on Chip, Digital communication, Synchronous systems, Latency insensitive, Input buffershttp://www.sciencedirect.com/science/article/pii/S2215098618315465 |
| spellingShingle | Mahdi Zare Fractional register calculation and optimization in scheduling based Latency-Insensitive design Engineering Science and Technology, an International Journal |
| title | Fractional register calculation and optimization in scheduling based Latency-Insensitive design |
| title_full | Fractional register calculation and optimization in scheduling based Latency-Insensitive design |
| title_fullStr | Fractional register calculation and optimization in scheduling based Latency-Insensitive design |
| title_full_unstemmed | Fractional register calculation and optimization in scheduling based Latency-Insensitive design |
| title_short | Fractional register calculation and optimization in scheduling based Latency-Insensitive design |
| title_sort | fractional register calculation and optimization in scheduling based latency insensitive design |
| url | http://www.sciencedirect.com/science/article/pii/S2215098618315465 |
| work_keys_str_mv | AT mahdizare fractionalregistercalculationandoptimizationinschedulingbasedlatencyinsensitivedesign |