Investigation on the Effects of Interconnect RC in 3nm Technology Node Using Path-Finding Process Design Kit

Investigation on the Effects of Interconnect RC in 3nm Technology Node Using Path-Finding Process Design Kit

With the continuous development of front-end-of-line (FEOL) technology, the development of interconnection processes at nanoscale process nodes is becoming important. We conducted a post-layout circuit simulation to consider the effect of parasitic R and C components of middle-of-Line (MOL) and back...

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Bibliographic Details
Main Authors: Yeji Lee, Wonyeong Jang, Kyungbae Kwon, Jihun Park, Changhyun Yoo, Jeesoo Chang, Jongwook Jeon
Format: Article
Language:English
Published: IEEE 2022-01-01
Series:IEEE Access
Subjects:
Gate-all-around FET
process design kit
parasitic extraction
benchmark
air spacer
Online Access:https://ieeexplore.ieee.org/document/9846989/

Internet

https://ieeexplore.ieee.org/document/9846989/

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