Low Latency YOLOv3-Tiny Accelerator for Low-Cost FPGA Using General Matrix Multiplication Principle

Low Latency YOLOv3-Tiny Accelerator for Low-Cost FPGA Using General Matrix Multiplication Principle

This paper presents a comprehensive hardware accelerator architecture of YOLOv3-Tiny targeted for low-cost FPGA with a high frame rate, high accuracy, and low latency. The proposed accelerator implements all YOLO layers in hardware including zero pad layer, convolution layer, leaky ReLU layer, batch...

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Bibliographic Details
Main Authors: Trio Adiono, Adiwena Putra, Nana Sutisna, Infall Syafalni, Rahmat Mulyawan
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Accelerator
GEMM
low-cost FPGA
YOLOv3-Tiny
Online Access:https://ieeexplore.ieee.org/document/9576092/

Internet

https://ieeexplore.ieee.org/document/9576092/

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