High Speed Delay-Locked Loop for Multiple Clock Phase Generation
In this paper, a high speed delay-locked loop (DLL) architecture is presented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which can be triggered by double edges of the i...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Shahid Rajaee Teacher Training University
2013-01-01
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| Series: | Journal of Electrical and Computer Engineering Innovations |
| Online Access: | https://jecei.sru.ac.ir/article_1661_93cf13c4f0f5b657d2e45cb6a7bec4e0.pdf |