High Speed Delay-Locked Loop for Multiple Clock Phase Generation
In this paper, a high speed delay-locked loop (DLL) architecture is presented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which can be triggered by double edges of the i...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Shahid Rajaee Teacher Training University
2013-01-01
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| Series: | Journal of Electrical and Computer Engineering Innovations |
| Online Access: | https://jecei.sru.ac.ir/article_1661_93cf13c4f0f5b657d2e45cb6a7bec4e0.pdf |
| _version_ | 1817993056492716032 |
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| author | A. Ghanbari A. Sadr M. Nikoo |
| author_facet | A. Ghanbari A. Sadr M. Nikoo |
| author_sort | A. Ghanbari |
| collection | DOAJ |
| description | In this paper, a high speed delay-locked loop (DLL) architecture is presented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which can be triggered by double edges of the input signals. In addition, the blind zone is removeddue to the elimination of reset signal. Therefore, operating frequency of the whole system is improved which can be mentioned as notable advantage of the proposed DLL. To obtain more accurate phases at the output signal, a new delay cell is introduced which is controlled by a single voltage. This control voltage, through equalizing the rise and fall time, regulate duty cycle of output clock. These features along with simplicity and low power consumption qualify the proposed architecture to be widely used in high speed systems. For better realization of the designed circuit’s behavior, simulation results are presented based on TSMC 0.35μm CMOS technology and 3.3-V power supply for a type II filter which demonstrate accuracy and perfect performance of this work. |
| first_indexed | 2024-04-14T01:34:41Z |
| format | Article |
| id | doaj.art-4d25b8014af24ba0939039f8ad3ec87d |
| institution | Directory Open Access Journal |
| issn | 2322-3952 2345-3044 |
| language | English |
| last_indexed | 2024-04-14T01:34:41Z |
| publishDate | 2013-01-01 |
| publisher | Shahid Rajaee Teacher Training University |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering Innovations |
| spelling | doaj.art-4d25b8014af24ba0939039f8ad3ec87d2022-12-22T02:20:02ZengShahid Rajaee Teacher Training UniversityJournal of Electrical and Computer Engineering Innovations2322-39522345-30442013-01-0111192710.22061/jecei.2013.16611661High Speed Delay-Locked Loop for Multiple Clock Phase GenerationA. Ghanbari0A. Sadr1M. Nikoo2Graduate School of Electrical Engineering, Qazvin Islamic Azad University (QIAU), Qazvin, IranDepartment of Electrical Engineering, Iran University of Science and Technology (IUST), Tehran, IranDepartment of Computer and Electrical Engineering, Islamic Azad University (MIAU)In this paper, a high speed delay-locked loop (DLL) architecture is presented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which can be triggered by double edges of the input signals. In addition, the blind zone is removeddue to the elimination of reset signal. Therefore, operating frequency of the whole system is improved which can be mentioned as notable advantage of the proposed DLL. To obtain more accurate phases at the output signal, a new delay cell is introduced which is controlled by a single voltage. This control voltage, through equalizing the rise and fall time, regulate duty cycle of output clock. These features along with simplicity and low power consumption qualify the proposed architecture to be widely used in high speed systems. For better realization of the designed circuit’s behavior, simulation results are presented based on TSMC 0.35μm CMOS technology and 3.3-V power supply for a type II filter which demonstrate accuracy and perfect performance of this work.https://jecei.sru.ac.ir/article_1661_93cf13c4f0f5b657d2e45cb6a7bec4e0.pdf |
| spellingShingle | A. Ghanbari A. Sadr M. Nikoo High Speed Delay-Locked Loop for Multiple Clock Phase Generation Journal of Electrical and Computer Engineering Innovations |
| title | High Speed Delay-Locked Loop for Multiple Clock Phase Generation |
| title_full | High Speed Delay-Locked Loop for Multiple Clock Phase Generation |
| title_fullStr | High Speed Delay-Locked Loop for Multiple Clock Phase Generation |
| title_full_unstemmed | High Speed Delay-Locked Loop for Multiple Clock Phase Generation |
| title_short | High Speed Delay-Locked Loop for Multiple Clock Phase Generation |
| title_sort | high speed delay locked loop for multiple clock phase generation |
| url | https://jecei.sru.ac.ir/article_1661_93cf13c4f0f5b657d2e45cb6a7bec4e0.pdf |
| work_keys_str_mv | AT aghanbari highspeeddelaylockedloopformultipleclockphasegeneration AT asadr highspeeddelaylockedloopformultipleclockphasegeneration AT mnikoo highspeeddelaylockedloopformultipleclockphasegeneration |