A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology
A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper. The main purposes of the proposed idea are to achieve high-resolution and high-speed SAR ADC simultaneousl...
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| Format: | Article |
| Language: | English |
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Shahid Rajaee Teacher Training University
2017-07-01
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| Series: | Journal of Electrical and Computer Engineering Innovations |
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| Online Access: | https://jecei.sru.ac.ir/article_693_55ae64050e3810aa5610ae0d6963c627.pdf |