A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage
We experimentally demonstrate a new type of silicon-based capacitorless one-transistor dynamic random access memory (1T-DRAM) with an electron-bridge channel. The fabrication steps are fully compatible with modern CMOS technology. An underlap device structure is exploited and positive charges are pr...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2017-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/7762150/ |
| _version_ | 1818369876980400128 |
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| author | Jyi-Tsong Lin Wei-Han Lee Po-Hsieh Lin Steve W. Haga Yun-Ru Chen Abhinav Kranti |
| author_facet | Jyi-Tsong Lin Wei-Han Lee Po-Hsieh Lin Steve W. Haga Yun-Ru Chen Abhinav Kranti |
| author_sort | Jyi-Tsong Lin |
| collection | DOAJ |
| description | We experimentally demonstrate a new type of silicon-based capacitorless one-transistor dynamic random access memory (1T-DRAM) with an electron-bridge channel. The fabrication steps are fully compatible with modern CMOS technology. An underlap device structure is exploited and positive charges are primarily stored in drain-side and source-side p-type pseudo-neutral regions under the oxide spacer. These regions are isolated by the gate/drain or gate/source depletion regions during programming and read “1” operations which facilitates the device to achieve a 4-second-long retention time at room temperature. The carrier mobility of the electron-bridge 1T-DRAM also exhibits reduced dependence on temperature, thereby the programming window remains viable at high temperatures, while also maintaining 26% of the retention performance at 358 K. The benefits of the planar cell enable the realization of a scalable vertical channel structure. |
| first_indexed | 2024-12-13T23:30:49Z |
| format | Article |
| id | doaj.art-4f754c5547b8407dbced11ab41908dec |
| institution | Directory Open Access Journal |
| issn | 2168-6734 |
| language | English |
| last_indexed | 2024-12-13T23:30:49Z |
| publishDate | 2017-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj.art-4f754c5547b8407dbced11ab41908dec2022-12-21T23:27:25ZengIEEEIEEE Journal of the Electron Devices Society2168-67342017-01-0151596310.1109/JEDS.2016.26332747762150A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge StorageJyi-Tsong Lin0https://orcid.org/0000-0002-0321-5424Wei-Han Lee1Po-Hsieh Lin2Steve W. Haga3Yun-Ru Chen4Abhinav Kranti5Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, TaiwanDepartment of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, TaiwanDepartment of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, TaiwanDepartment of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, TaiwanDepartment of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, TaiwanLow Power Nanoelectronics Research Group, Discipline of Electrical Engineering, Institute of Technology Indore, Simrol, IndiaWe experimentally demonstrate a new type of silicon-based capacitorless one-transistor dynamic random access memory (1T-DRAM) with an electron-bridge channel. The fabrication steps are fully compatible with modern CMOS technology. An underlap device structure is exploited and positive charges are primarily stored in drain-side and source-side p-type pseudo-neutral regions under the oxide spacer. These regions are isolated by the gate/drain or gate/source depletion regions during programming and read “1” operations which facilitates the device to achieve a 4-second-long retention time at room temperature. The carrier mobility of the electron-bridge 1T-DRAM also exhibits reduced dependence on temperature, thereby the programming window remains viable at high temperatures, while also maintaining 26% of the retention performance at 358 K. The benefits of the planar cell enable the realization of a scalable vertical channel structure.https://ieeexplore.ieee.org/document/7762150/Capacitorless 1T-DRAMsilicon-on-insulator technologyelectron-bridge |
| spellingShingle | Jyi-Tsong Lin Wei-Han Lee Po-Hsieh Lin Steve W. Haga Yun-Ru Chen Abhinav Kranti A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage IEEE Journal of the Electron Devices Society Capacitorless 1T-DRAM silicon-on-insulator technology electron-bridge |
| title | A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage |
| title_full | A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage |
| title_fullStr | A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage |
| title_full_unstemmed | A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage |
| title_short | A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage |
| title_sort | new electron bridge channel 1t dram employing underlap region charge storage |
| topic | Capacitorless 1T-DRAM silicon-on-insulator technology electron-bridge |
| url | https://ieeexplore.ieee.org/document/7762150/ |
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