Junctionless Biristor: A Bistable Resistor Without Chemically Doped P-N Junctions

In this paper, using 2-D simulations, we report a novel junction-less biristor in which the emitter and collector regions are created by applying the charge plasma concept on a P-doped silicon film. Since no chemical doping is required, the junction-less biristor can be realized with a low thermal b...

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Main Authors: Mamidala Jagadesh Kumar, Maram Maheedhar, P. Pradeep Varma
Format: Article
Language:English
Published: IEEE 2015-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Online Access:https://ieeexplore.ieee.org/document/7076587/
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author Mamidala Jagadesh Kumar
Maram Maheedhar
P. Pradeep Varma
author_facet Mamidala Jagadesh Kumar
Maram Maheedhar
P. Pradeep Varma
author_sort Mamidala Jagadesh Kumar
collection DOAJ
description In this paper, using 2-D simulations, we report a novel junction-less biristor in which the emitter and collector regions are created by applying the charge plasma concept on a P-doped silicon film. Since no chemical doping is required, the junction-less biristor can be realized with a low thermal budget. We demonstrate that the junction-less biristor exhibits not only a significant low latch-up voltage (2.0 V) but also has a large latch window (0.66 V) when compared to that of a conventional silicon biristor with similar parameters. The reasons for this improved performance are discussed.
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spelling doaj.art-52a32ef62ef7468b8167f138716f0bd82022-12-21T22:22:40ZengIEEEIEEE Journal of the Electron Devices Society2168-67342015-01-013431131510.1109/JEDS.2015.24187547076587Junctionless Biristor: A Bistable Resistor Without Chemically Doped P-N JunctionsMamidala Jagadesh Kumar0Maram Maheedhar1P. Pradeep Varma2Department of Electrical Engineering, Indian Institute of Technology, New Delhi, IndiaDepartment of Electrical Engineering, Indian Institute of Technology, New Delhi, IndiaDepartment of Electrical Engineering, Indian Institute of Technology, New Delhi, IndiaIn this paper, using 2-D simulations, we report a novel junction-less biristor in which the emitter and collector regions are created by applying the charge plasma concept on a P-doped silicon film. Since no chemical doping is required, the junction-less biristor can be realized with a low thermal budget. We demonstrate that the junction-less biristor exhibits not only a significant low latch-up voltage (2.0 V) but also has a large latch window (0.66 V) when compared to that of a conventional silicon biristor with similar parameters. The reasons for this improved performance are discussed.https://ieeexplore.ieee.org/document/7076587/biristorjunction-lessbistable resistorcurrent gainSALTran effect
spellingShingle Mamidala Jagadesh Kumar
Maram Maheedhar
P. Pradeep Varma
Junctionless Biristor: A Bistable Resistor Without Chemically Doped P-N Junctions
IEEE Journal of the Electron Devices Society
biristor
junction-less
bistable resistor
current gain
SALTran effect
title Junctionless Biristor: A Bistable Resistor Without Chemically Doped P-N Junctions
title_full Junctionless Biristor: A Bistable Resistor Without Chemically Doped P-N Junctions
title_fullStr Junctionless Biristor: A Bistable Resistor Without Chemically Doped P-N Junctions
title_full_unstemmed Junctionless Biristor: A Bistable Resistor Without Chemically Doped P-N Junctions
title_short Junctionless Biristor: A Bistable Resistor Without Chemically Doped P-N Junctions
title_sort junctionless biristor a bistable resistor without chemically doped p n junctions
topic biristor
junction-less
bistable resistor
current gain
SALTran effect
url https://ieeexplore.ieee.org/document/7076587/
work_keys_str_mv AT mamidalajagadeshkumar junctionlessbiristorabistableresistorwithoutchemicallydopedpnjunctions
AT marammaheedhar junctionlessbiristorabistableresistorwithoutchemicallydopedpnjunctions
AT ppradeepvarma junctionlessbiristorabistableresistorwithoutchemicallydopedpnjunctions