Research on short-circuit dissipation in master-slaver D flip-flop(主从型D触发器中短路功耗的研究)

在对主从型D触发器分析短路功耗的基础上,本文提出了一种使D触发器工作在两个有一定相位差的时钟下以减少ID触发器短路功耗的方法.模拟结果证明了该方法的有效性.

Bibliographic Details
Main Authors:	WANGLun yao(王伦耀), WUXun-wei(吴训威)
Format:	Article
Language:	zho
Published:	Zhejiang University Press 2003-07-01
Series:	Zhejiang Daxue xuebao. Lixue ban
Subjects:	低功耗主从型d触发器 cmos电路
Online Access:	https://doi.org/zjup/1008-9497.2003.30.4.409-412

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