A 21.4 pW Subthreshold Voltage Reference with 0.020 %/V Line Sensitivity Using DIBL Compensation
This paper presents an ultra-low-power voltage reference designed in 180 nm CMOS technology. To achieve near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased with a current source to cancel the drain-induced barrier-lowering (DIBL) effect of the 2-T core, thus improving the...
Main Authors: | , , |
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Format: | Article |
Language: | English |
Published: |
MDPI AG
2023-02-01
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Series: | Sensors |
Subjects: | |
Online Access: | https://www.mdpi.com/1424-8220/23/4/1862 |