A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver

A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver

This paper presents a dedicated digital signal process (DSP) for four pulse amplitude modulation (PAM4) SerDes receivers. It is targeted to implement data recovery and adaptive equalization under ultra-high-speed and large channel attenuation with a small area and high power efficiency. The DSP cons...

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Bibliographic Details
Main Authors: Weijie Li, Min Liu, Xuqiang Zheng, Guangxing Xiao, Guojun Yuan, Qinfen Hao, Zhi Jin
Format: Article
Language:English
Published: MDPI AG 2023-01-01
Series:Electronics
Subjects:
digital signal process (DSP)
wireline transceiver
feed forward equalizer (FFE)
decision feedback equalizer (DFE)
parallel
multiplexer (MUX)
Online Access:https://www.mdpi.com/2079-9292/12/2/257

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https://www.mdpi.com/2079-9292/12/2/257

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