Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems

Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems

This paper presents an approach for reducing the memory requirements of periodically executed dataflow applications, while minimizing the period when deployed on a many-core target. Often, implementations of dataflow applications suffer from data duplication if identical data has to be processed by...

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Bibliographic Details
Main Authors: Martin Letras, Joachim Falk, Jurgen Teich
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
Many-core systems
dataflow networks
mapping
Pareto optimization
memory management
modulo scheduling
Online Access:https://ieeexplore.ieee.org/document/10463021/

Internet

https://ieeexplore.ieee.org/document/10463021/

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