Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems
This paper presents an approach for reducing the memory requirements of periodically executed dataflow applications, while minimizing the period when deployed on a many-core target. Often, implementations of dataflow applications suffer from data duplication if identical data has to be processed by...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10463021/ |
| _version_ | 1797243289388187648 |
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| author | Martin Letras Joachim Falk Jurgen Teich |
| author_facet | Martin Letras Joachim Falk Jurgen Teich |
| author_sort | Martin Letras |
| collection | DOAJ |
| description | This paper presents an approach for reducing the memory requirements of periodically executed dataflow applications, while minimizing the period when deployed on a many-core target. Often, implementations of dataflow applications suffer from data duplication if identical data has to be processed by multiple actors. In fact, multi-cast (also called fork) actors can produce huge memory overheads when storing and communicating copies of the same data. As a remedy, so-called Multi-Reader Buffers (MRBs) can be utilized to forward identical data to multiple actors in a First In First Out (FIFO) manner while storing each data item only once by sharing. However, using MRBs may increase the achievable period due to contention when accessing the shared data. This paper proposes a novel multi-objective design space exploration approach that selectively replaces multi-cast actors with MRBs and explores actor and FIFO channel mappings to find trade-offs between the objectives of period, memory footprint, and core cost. In distinction to the state-of-the-art, our approach considers (i) memory-size constraints for on-chip memories, (ii) hierarchical memories to implement the buffers, e.g., tile-local memories, (iii) supports heterogeneous many-core platforms, i.e., core-type dependent actor execution times, and (iv) optimizes the buffer placement and overall scheduling to minimize the execution period by proposing a novel combined actor and communication scheduling heuristic for period minimization called Communication-Aware Periodic Scheduling on Heterogeneous Many-core Systems (CAPS-HMS). Our results show that the explored Pareto fronts improve a hypervolume indicator over a reference approach by up to 66 % for small to mid-size applications and 90 % for large applications. Moreover, selectively replacing multi-cast actors with corresponding MRBs proves to be always superior to never or always replacing them. Finally, it is shown that the quality of the explored Pareto fronts does not degrade when replacing the efficient scheduling heuristic CAPS-HMS by an Integer Linear Program (ILP) solver that requires orders of magnitude higher solver times and thus cannot be applied to large scale dataflow network problems. |
| first_indexed | 2024-04-24T18:52:45Z |
| format | Article |
| id | doaj.art-572379ddeeee4da685128d4115cdbc1c |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-24T18:52:45Z |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-572379ddeeee4da685128d4115cdbc1c2024-03-26T17:47:48ZengIEEEIEEE Access2169-35362024-01-0112397483976910.1109/ACCESS.2024.337507910463021Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core SystemsMartin Letras0https://orcid.org/0000-0002-1429-8982Joachim Falk1https://orcid.org/0009-0006-0834-3237Jurgen Teich2https://orcid.org/0000-0001-6285-5862Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, GermanyDepartment of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, GermanyDepartment of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, GermanyThis paper presents an approach for reducing the memory requirements of periodically executed dataflow applications, while minimizing the period when deployed on a many-core target. Often, implementations of dataflow applications suffer from data duplication if identical data has to be processed by multiple actors. In fact, multi-cast (also called fork) actors can produce huge memory overheads when storing and communicating copies of the same data. As a remedy, so-called Multi-Reader Buffers (MRBs) can be utilized to forward identical data to multiple actors in a First In First Out (FIFO) manner while storing each data item only once by sharing. However, using MRBs may increase the achievable period due to contention when accessing the shared data. This paper proposes a novel multi-objective design space exploration approach that selectively replaces multi-cast actors with MRBs and explores actor and FIFO channel mappings to find trade-offs between the objectives of period, memory footprint, and core cost. In distinction to the state-of-the-art, our approach considers (i) memory-size constraints for on-chip memories, (ii) hierarchical memories to implement the buffers, e.g., tile-local memories, (iii) supports heterogeneous many-core platforms, i.e., core-type dependent actor execution times, and (iv) optimizes the buffer placement and overall scheduling to minimize the execution period by proposing a novel combined actor and communication scheduling heuristic for period minimization called Communication-Aware Periodic Scheduling on Heterogeneous Many-core Systems (CAPS-HMS). Our results show that the explored Pareto fronts improve a hypervolume indicator over a reference approach by up to 66 % for small to mid-size applications and 90 % for large applications. Moreover, selectively replacing multi-cast actors with corresponding MRBs proves to be always superior to never or always replacing them. Finally, it is shown that the quality of the explored Pareto fronts does not degrade when replacing the efficient scheduling heuristic CAPS-HMS by an Integer Linear Program (ILP) solver that requires orders of magnitude higher solver times and thus cannot be applied to large scale dataflow network problems.https://ieeexplore.ieee.org/document/10463021/Many-core systemsdataflow networksmappingPareto optimizationmemory managementmodulo scheduling |
| spellingShingle | Martin Letras Joachim Falk Jurgen Teich Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems IEEE Access Many-core systems dataflow networks mapping Pareto optimization memory management modulo scheduling |
| title | Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems |
| title_full | Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems |
| title_fullStr | Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems |
| title_full_unstemmed | Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems |
| title_short | Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems |
| title_sort | exploring multi reader buffers and channel placement during dataflow network mapping to heterogeneous many core systems |
| topic | Many-core systems dataflow networks mapping Pareto optimization memory management modulo scheduling |
| url | https://ieeexplore.ieee.org/document/10463021/ |
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