High Speed and Less Area Efficient Montgomery Modular Multiplication for VLSI Applications
A high speed and area efficient Montgomery modular multiplication algorithm is implemented. In the proposed multiplier high speed is achieved by using the carry save adder (CSA) to reduce the carry propagation at the addition operation stage due to this delay is reduced and the input and outputs are...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
EDP Sciences
2024-01-01
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| Series: | E3S Web of Conferences |
| Subjects: | |
| Online Access: | https://www.e3s-conferences.org/articles/e3sconf/pdf/2024/70/e3sconf_icpes2024_14003.pdf |