DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

DFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications

The device dimensions have been consistently scaling down since many developing technologies need smaller and faster integrated circuits for advancement and improvement in both performance and device density. Device dimensions have been decreased drastically from micron to sub nanometer regime. Trad...

Full description

Bibliographic Details
Main Authors:	Bhoop Singh, Prasad B, Dinesh Kumar
Format:	Article
Language:	English
Published:	IOP Publishing 2020-01-01
Series:	Materials Research Express
Subjects:	DFT GAA CNTFET FinFET Chirality MedeA
Online Access:	https://doi.org/10.1088/2053-1591/ab6924

Similar Items

Comparative Study of Novel u-Shaped SOI FinFET Against Multiple-Fin Bulk/SOI FinFET
by: Myoungsu Son, et al.
Published: (2023-01-01)

Reliability analysis of a CNT-TF-FinFET for hostile temperature
by: Praween Kumar Srivastava, et al.
Published: (2023-12-01)

An Efficient Technique to Simulate the AC/DC Parameters of Trigate FinFETs
by: Qamar-Ud-Din Memon, et al.
Published: (2024-01-01)

Comprehensive analysis of In0.53Ga0.47As SOI-FinFET for enhanced RF/wireless performance
by: Priyanka Agrwal, et al.
Published: (2025-02-01)

Performance assessment of InGaAs–SOI–FinFET for enhancing switching capability using high-k dielectric
by: Priyanka Agrwal, et al.
Published: (2024-08-01)

Review of Nanosheet Transistors Technology
by: Firas N. A. Hassan Agha, et al.
Published: (2021-05-01)

Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET
by: Soohyun Kim, et al.
Published: (2020-04-01)

Dual Material Pile Gate Approach for Low Leakage Finfet
by: Sanjay S. Chopade, et al.
Published: (2017-01-01)

Analysis of Threshold Voltage Flexibility in Ultrathin-BOX SOI FinFETs
by: Kazuhiko Endo, et al.
Published: (2014-05-01)

A Dual Core Source/Drain GAA FinFET
by: Prachuryya Subash Das, et al.
Published: (2023-06-01)

The Impact of Hysteresis Effect on Device Characteristic and Reliability for Various Fin-Widths Tri-Gate Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> Ferroelectric FinFET
by: Wen-Qi Zhang, et al.
Published: (2023-04-01)

Novel Second-Order Fully Differential All-Pass Filter Using CNTFETs
by: Muhammad I. Masud, et al.
Published: (2023-09-01)

Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield
by: Koji Sakui, et al.
Published: (2023-07-01)

Unravelling the Potential of Density Functional Theory through Integrated Computational Environments: Recent Applications of the Vienna Ab Initio Simulation Package in the MedeA<sup>®</sup> Software
by: Volker Eyert, et al.
Published: (2018-12-01)

BSIM—SPICE Models Enable FinFET and UTB IC Designs
by: Navid Paydavosi, et al.
Published: (2013-01-01)

Performance evaluation of SRAM design using different field effect transistors
by: C. Venkataiah, et al.
Published: (2023-01-01)

Design of improved write and read performance 12T sram cell with leakage power control technique
by: M. Srinu, et al.
Published: (2024-06-01)

Investigation of Single-Event Upset in Graphene Nano-Ribbon FET SRAM Cell
by: Naheem Olakunle Adesina
Published: (2023-07-01)

Optimization of Multi-Fins FinFET Implemented on SOI Wafer Based on SiGe and Gaussian Process Regression
by: Christofer N. Yalung, et al.
Published: (2024-01-01)

Simulation of Novel Nano Low-Dimensional FETs at the Scaling Limit
by: Pengwen Guo, et al.
Published: (2024-08-01)

High-Performance and Energy-Efficient Leaky Integrate-and-Fire Neuron and Spike Timing-Dependent Plasticity Circuits in 7nm FinFET Technology
by: Mohammad Khaleqi Qaleh Jooq, et al.
Published: (2023-01-01)

Process Corresponding Implications Associated with a Conclusive Model-Fit Current-Voltage Characteristic Curves
by: Hsin-Chia Yang, et al.
Published: (2022-01-01)

Silicon-Controlled Rectifier Embedded Diode for 7 nm FinFET Process Electrostatic Discharge Protection
by: Xinyu Zhu, et al.
Published: (2022-05-01)

The Challenges of Advanced CMOS Process from 2D to 3D
by: Henry H. Radamson, et al.
Published: (2017-10-01)

3D Simulation for Melt Laser Anneal Integration in FinFET’s Contact
by: Toshiyuki Tabata, et al.
Published: (2020-01-01)

Miniaturization of CMOS
by: Henry H. Radamson, et al.
Published: (2019-04-01)

Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology
by: Anil Kumar Bansal, et al.
Published: (2016-01-01)

Design and analysis of multichannel 10 nm nanosheet FinFET varying space region materials and doping concentrations
by: Hima Bindu Valiveti, et al.
Published: (2024-12-01)

High-Drain Field Impacting Channel-Length Modulation Effect for Nano-Node N-Channel FinFETs
by: Mu-Chun Wang, et al.
Published: (2021-03-01)

Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO<sub>2</sub> for Sub-60-mV/Decade Subthreshold Slope for Low Power Application
by: Siao-Cheng Yan, et al.
Published: (2022-06-01)

Impact of changing channel length and band gaps of a carbon nanotube on the current of a Carbon Nanotube Field Effect Transistors (CNTFETs)
by: Khoder Bachour, et al.
Published: (2020-03-01)

Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics
by: Yongliang Li, et al.
Published: (2021-06-01)

Design and Analysis of Self-Tanked Stepwise Charging Circuit for Four-Phase Adiabatic Logic
by: William Morell, et al.
Published: (2024-06-01)

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA
by: Justin Sobas, et al.
Published: (2023-12-01)

Simulation Study on the Charge Collection Mechanism of FinFET Devices in Single-Event Upset
by: Hongwei Zhang, et al.
Published: (2024-01-01)

Combining Chemical Functionalization and FinFET Geometry for Field Effect Sensors as Accessible Technology to Optimize pH Sensing
by: Dipti Rani, et al.
Published: (2021-01-01)

Investigation of the Integration of Strained Ge Channel with Si-Based FinFETs
by: Buqing Xu, et al.
Published: (2022-04-01)

Embedded Micro-detectors for EUV Exposure Control in FinFET CMOS Technology
by: Chien-Ping Wang, et al.
Published: (2022-01-01)

A Unified Depletion/Inversion Model for Heterojunction Trigate FinFETs DC Characteristics
by: Qamar-Ud-Din Memon, et al.
Published: (2021-01-01)

An Experimental Approach to Characterizing the Channel Local Temperature Induced by Self-Heating Effect in FinFET
by: E Ray Hsieh, et al.
Published: (2018-01-01)