A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting

A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting

Increasing the size of target arrays is beneficial to reuse fault-free processing elements (PEs) for reconfiguring 2-D mesh-connected processor arrays with faults. In this paper, we discuss the reconfiguration problem under the row and column rerouting constraint. We present a novel approach, making...

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Bibliographic Details
Main Authors: Junyan Qian, Yiping Wang, Liang Chang, Zhide Zhou, Lingzhong Zhao
Format: Article
Language:English
Published: IEEE 2017-01-01
Series:IEEE Access
Subjects:
Integer programming
fault tolerance
reconfiguration
processor array
algorithm
Online Access:https://ieeexplore.ieee.org/document/8076838/

Internet

https://ieeexplore.ieee.org/document/8076838/

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