A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting
Increasing the size of target arrays is beneficial to reuse fault-free processing elements (PEs) for reconfiguring 2-D mesh-connected processor arrays with faults. In this paper, we discuss the reconfiguration problem under the row and column rerouting constraint. We present a novel approach, making...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2017-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/8076838/ |
| _version_ | 1818370145406418944 |
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| author | Junyan Qian Yiping Wang Liang Chang Zhide Zhou Lingzhong Zhao |
| author_facet | Junyan Qian Yiping Wang Liang Chang Zhide Zhou Lingzhong Zhao |
| author_sort | Junyan Qian |
| collection | DOAJ |
| description | Increasing the size of target arrays is beneficial to reuse fault-free processing elements (PEs) for reconfiguring 2-D mesh-connected processor arrays with faults. In this paper, we discuss the reconfiguration problem under the row and column rerouting constraint. We present a novel approach, making use of the idea of integer programming, for constructing larger size target arrays. Meanwhile, we propose a new method to deal with the fault-free processing elements in the physical row that is selected for exclusion. Compared with the state-of-arts algorithms, our method can make the fault-free PEs used as much as possible, which means the size of the target array can be significantly improved. Experimental results show that, compared with previous studies, the proposed algorithm achieves better results in terms of the usage rate of fault-free PEs in the host array. |
| first_indexed | 2024-12-13T23:35:05Z |
| format | Article |
| id | doaj.art-58d017e0c71c4ea0be9a5eec5769507f |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-13T23:35:05Z |
| publishDate | 2017-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-58d017e0c71c4ea0be9a5eec5769507f2022-12-21T23:27:20ZengIEEEIEEE Access2169-35362017-01-015239122391910.1109/ACCESS.2017.27650848076838A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column ReroutingJunyan Qian0https://orcid.org/0000-0002-1325-6975Yiping Wang1Liang Chang2Zhide Zhou3Lingzhong Zhao4Guangxi Key Laboratory of Trusted Software, Guilin University of Electronic Technology, Guilin, ChinaGuangxi Key Laboratory of Trusted Software, Guilin University of Electronic Technology, Guilin, ChinaGuangxi Key Laboratory of Trusted Software, Guilin University of Electronic Technology, Guilin, ChinaGuangxi Key Laboratory of Trusted Software, Guilin University of Electronic Technology, Guilin, ChinaGuangxi Key Laboratory of Trusted Software, Guilin University of Electronic Technology, Guilin, ChinaIncreasing the size of target arrays is beneficial to reuse fault-free processing elements (PEs) for reconfiguring 2-D mesh-connected processor arrays with faults. In this paper, we discuss the reconfiguration problem under the row and column rerouting constraint. We present a novel approach, making use of the idea of integer programming, for constructing larger size target arrays. Meanwhile, we propose a new method to deal with the fault-free processing elements in the physical row that is selected for exclusion. Compared with the state-of-arts algorithms, our method can make the fault-free PEs used as much as possible, which means the size of the target array can be significantly improved. Experimental results show that, compared with previous studies, the proposed algorithm achieves better results in terms of the usage rate of fault-free PEs in the host array.https://ieeexplore.ieee.org/document/8076838/Integer programmingfault tolerancereconfigurationprocessor arrayalgorithm |
| spellingShingle | Junyan Qian Yiping Wang Liang Chang Zhide Zhou Lingzhong Zhao A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting IEEE Access Integer programming fault tolerance reconfiguration processor array algorithm |
| title | A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting |
| title_full | A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting |
| title_fullStr | A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting |
| title_full_unstemmed | A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting |
| title_short | A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting |
| title_sort | mathematical model for reconfiguring vlsi subarrays under row and column rerouting |
| topic | Integer programming fault tolerance reconfiguration processor array algorithm |
| url | https://ieeexplore.ieee.org/document/8076838/ |
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